This invention relates to the fabrication of complementary metal oxide semiconductor (CMOS) integrated circuits. More particularly, this invention relates to the fabrication of CMOS integrated circuits (IC's) having a reduced contact resistance when such IC's are fabricated using a plasma to etch vias (openings) in the glass insulating layers thereof.
When an integrated circuit chip is fabricated, it is one of many chips, arranged in an orderly array on a wafer of semiconductor material. When all of the circuit components, i.e., transistors, resistors, etc., have been formed on the wafer, it is coated with a thin layer of glass. Openings, called "vias," are then etched in the glass layer at selected points to expose elements of selected circuit components.
The circuit components are then interconnected to form circuits which perform the desired functions. The interconnections are made by depositing metal traces, in the desired pattern, between the vias. As the metal traces are being deposited on the glass layer, metal is also being deposited on the sides and bottom of the vias, forming an electrical connection between elements of circuit components. During this deposition process, the layer of glass acts as an insulation between the metal traces and the wafer. In many cases, more than one layer of metal traces is required to form all the interconnections necessary. In such cases, a layer of glass is formed over the previous layer of metal traces, vias are etched down to the wafer, and the next layer of metal traces is deposited. The details of the process of fabricating integrated circuits are, for purposes of this application, well understood in the art. Accordingly, other than for the process of etching vias, which is the subject of the present invention, no further explanation will be given herein.
In the prior art, before the integrated circuit technology advanced to what is now called very large scale integration (VLSI), a wet chemical, e.g., hydrofluoric (HF) acid was used to etch vias through the insulating glass layer(s). This process has an inherent disadvantage in that as the HF etches down into the glass, it also etches away the sides of the via. Thus, in forming an opening of a given size at the bottom of the glass (at the surface of the wafer), a much larger opening must be made at the top surface of the glass. A "wet-etched" via typically has, therefore, a "V" cross-sectional shape associated therewith.
As integrated circuit density increased to VLSI, the dimensions of the circuits, vias etc., decreased to the point where a wet chemical process could not be used for etching vias because the larger opening at the top of the via interfered with the area to be used for wiring traces or with other vias. Therefore, wet etching of vias was a major impediment to the development of VLSI integrated circuits and much time and effort was spent to find a process that produced vias with nearly vertical sides.
The solution found and presently used in the art to produce vias with nearly vertical sides is to use a plasma for etching the vias. In this process, the wafer is placed in an atmosphere of the appropriate gasses. The gasses are heated and excited by a radio frequently (RF) field to form a plasma. The plasma etches the via by both chemically reacting with the glass and by ion bombardment. Because of the RF field, the direction of etch is nearly straight down through the glass, and a via is formed whose top and bottom openings are very nearly the same size.
In CMOS technology, the etching process exposes both N+ elements of N channel transistors and P+ elements of P channel transistors. (The "+" and "-" signs refer to the relative doping of a given semiconductor material, and the "P" and "N" refer to the polarity of this doping.) Disadvantageously, plasma etching damages the surface of the N+ elements. The damage is primarily a disruption of the crystal lattice structure of the N+ material, and is believed to be caused by the plasma reacting more with the dopant used to form the N+ material in the silicon rather than reacting with the silicon itself. If not corrected, this reaction or damage adds resistance in the circuit formed by the subsequent wiring steps, which added resistance (commonly referred to as "contact resistance") disadvantageously slows down the performance of the circuit. Both rise and fall times as well as circuit delays are affected by the additional resistance. Since it is desirable to have integrated circuits perform their respective functions as fast as possible, the presence of this resistance is a process problem that must be corrected.
An obvious solution to this problem of added resistance would be to subject the wafer to a diffusion step that diffuses the dopant material back into the N+ region, thereby reducing the resistance. However, in CMOS, both N+ and P+ elements are simultaneously exposed, and the diffusion process would contaminate the P+ region unless preventative steps are taken. Thus, in order to correct the problem of added resistance, additional process steps of masking the vias over the P+ region, diffusing dopant into the N+ region, and removing the masking material would have to be followed. Not only do these additional process steps represent added expense and time, there is a good possibility that some of the masking material would remain in the vias over the P+ material, causing faulty electrical connections.
Another, more common solution known in the art to the problem of the added contact resistance is to follow a process that prevents it from occurring. This is done by using the plasma etch to form part of the via, but stopping the process before the plasma etches all the way through to the glass layer. The wafer is then subjected to an HF etch to complete the via. This solution, however, as explained below, is not suitable for use with CMOS technology.
In CMOS technology, a thin layer of silicon dioxide is formed over the N+ and P+ elements to act as an insulator for the gate before the glass layer is added. The HF must also etch through the silicon dioxide layer in order to expose the N+ and P+ elements. Unfortunately, the HF etches the glass approximately ten times faster than it etches the silicon dioxide. Thus, as the HF completes the process of opening the via, through the silicon dioxide, it is also etching into the sides of the via, undesirably widening the via as described above.
Hence, while the combined process of using plasma and HF etching results in a via smaller than those obtained by HF etching alone, the vias are nonetheless larger than if only plasma etching were used. Thus, by using a process that avoids forming the undesirable contact resistance, the density of the circuits that can be formed is restricted, since the top openings of the vias are wider than the bottom openings.
From the above discussion it is evident that there is a need in the art of CMOS technology for a process that allows the advantage of plasma etching of vias without having to introduce a multiplicity of additional process steps. The present invention is directed to that need.